Silicon Labs /SiM3_NRND /SIM3U166_B /CLKCTRL_0 /APBCLKG1

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Interpret as APBCLKG1

MISC0CEN=DISABLED, MISC2CEN=DISABLED, MISC1CEN=DISABLED

Description

APB Clock Gate 1

Fields

MISC0CEN	Miscellaneous 0 Clock Enable. 0 (DISABLED): Disable the APB clock to the RSTSRC0, LOCK0, VMON0, VREG0, LDO0, VREF0, EXTOSC0, LPOSC0, EXTVREG0, IVC0 and RTC0 modules (default). 1 (ENABLED): Enable the APB clock to the RSTSRC0, LOCK0, VMON0, VREG0, LDO0, VREF0, EXTOSC0, LPOSC0, EXTVREG0, IVC0 and RTC0 modules.
MISC1CEN	Miscellaneous 1 Clock Enable. 0 (DISABLED): Disable the APB clock to the Watchdog Timer (WDTIMER0), EMIF0, and DMA Crossbar (DMAXBAR0) modules. 1 (ENABLED): Enable the APB clock to the Watchdog Timer (WDTIMER0), EMIF0, and DMA Crossbar (DMAXBAR0) modules (default).
MISC2CEN	Miscellaneous 2 Clock Enable. 0 (DISABLED): Disable the APB clock to the OSCVLDF flag in the EXTOSC module (default). 1 (ENABLED): Enable the APB clock to the OSCVLDF flag in the EXTOSC module.

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